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LPC2292/LPC2294
16/32-bit ARM microcontrollers; 256 kB ISP/IAP Flash with CAN, 10-bit ADC and external memory interface
Rev. 01 -- 05 February 2004 Preliminary data
1. General description
The LPC2292/LPC2294 are based on a 16/32 bit ARM7TDMI-STM CPU with real-time emulation and embedded trace support, together with 256 kilobytes (kB) of embedded high speed flash memory. A 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at maximum clock rate. For critical code size applications, the alternative 16-bit Thumb Mode reduces code by more than 30% with minimal performance penalty. With their 144 pin package, low power consumption, various 32-bit timers, 8-channel 10-bit ADC, 2/4 (LP2292/LPC2294) advanced CAN channels, PWM channels and up to 9 external interrupt pins these microcontrollers are particularly suitable for automotive and industrial control applications as well as medical systems and fault-tolerant maintenance buses. Number of available GPIOs ranges from 76 (with external memory) through 112 (single-chip). With a wide range of additional serial communications interfaces, they are also suited for communication gateways and protocol converters as well as many other general-purpose applications.
2. Features
2.1 Key features
s 16/32-bit ARM7TDMI-S microcontroller in a LQFP144 package. s 16 kB on-chip Static RAM and 256 kB on-chip Flash Program Memory. 128-bit wide interface/accelerator enables high speed 60 MHz operation. s In-System Programming (ISP) and In-Application Programming (IAP) via on-chip boot-loader software. Flash programming takes 1 ms per 512 byte line. Single sector or full chip erase takes 400 ms. s EmbeddedICE-RT and Embedded Trace interfaces offer real-time debugging with the on-chip RealMonitor software as well as high speed real-time tracing of instruction execution. s Two/four (LPC2292/2294) interconnected CAN interfaces with advanced acceptance filters. Additional serial interfaces include two UARTs (16C550), Fast I2C (400 kbits/s) and two SPIsTM. s Eight channel 10-bit A/D converter with conversion time as low as 2.44 s. s Two 32-bit timers (with 4 capture and 4 compare channels), PWM unit (6 outputs), Real Time Clock and Watchdog. s Vectored Interrupt Controller with configurable priorities and vector addresses. s Configurable external memory interface with up to four banks, each up to 16 Mb and 8/16/32 bit data width. s Up to 112 general purpose I/O pins (5 V tolerant). Up to 9 edge/level sensitive external interrupt pins available.
Philips Semiconductors
LPC2292/LPC2294
16/32-bit ARM microcontrollers with external memory interface
s 60 MHz maximum CPU clock available from programmable on-chip Phase-Locked Loop. s On-chip crystal oscillator with an operating range of 1 MHz to 30 MHz. s Two low power modes, Idle and Power-down. s Processor wake-up from Power-down mode via external interrupt. s Individual enable/disable of peripheral functions for power optimization. s Dual power supply: x CPU operating voltage range of 1.65 V to 1.95 V (1.8 V 0.15 V). x I/O power supply range of 3.0 V to 3.6 V (3.3 V 10%) with 5 V tolerant I/O pads.
3. Ordering information
Table 1: Ordering information Package Name LPC2292FBD144 LQFP144 LPC2294JBD144 LQFP144 Description plastic low profile quad flat package, 144 leads, body 20 x 20 x 1.4 mm plastic low profile quad flat package, 144 leads, body 20 x 20 x 1.4 mm Version SOT486-1 SOT486-1 Type number
3.1 Ordering options
Table 2: Part options Flash memory 256 kB 256 kB RAM 16 kB 16 kB CAN 2 channels 4 channels Temperature range (C) -40 to +85 -40 to +125 Type number LPC2292FBD144 LPC2294JBD144
9397 750 12748
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data
Rev. 01 -- 05 February 2004
2 of 40
Philips Semiconductors
LPC2292/LPC2294
16/32-bit ARM microcontrollers with external memory interface
4. Block diagram
TRST(1) TMS(1) TCK(1) TDI(1) TDO(1)
TEST/DEBUG INTERFACE
EMULATION TRACE MODULE
PLL system clock
SYSTEM FUNCTIONS
ARM7TDMI-S
AHB BRIDGE ARM7 LOCAL BUS
VECTORED INTERRUPT CONTROLLER
AMBA AHB (Advanced High-performance Bus)
INTERNAL SRAM CONTROLLER
INTERNAL FLASH CONTROLLER AHB TO VPB VPB BRIDGE DIVIDER VPB (VLSI peripheral bus)
AHB DECODER CS3:0* A23:0* BLS3:0* OE, WE* D31:0* SCL SDA
16 kB SRAM
128/256 kB FLASH
EXTERNAL MEMORY CONTROLLER
EINT3:0
EXTERNAL INTERRUPTS
I2C SERIAL INTERFACE
8 x CAP0 8 x MAT
SCK0,1 CAPTURE/ COMPARE TIMER 0 & 1 SPI SERIAL INTERFACES 0 & 1 MOSI0,1 MISO0,1 SSEL0,1 TxD0,1 A/D CONVERTER RxD0,1 UART 0 & 1
DSR1,CTS1, DCD1, RI1
Ain3:0 Ain7:4
P0.30:0 P1.31:16, 1:0 P2.31:0 P3.31:0 GENERAL PURPOSE I/O CAN
TD2:1 RD2:1 TD4:3(2) RD4:3(2)
PWM6:1
PWM0
WATCHDOG TIMER
REAL TIME CLOCK
SYSTEM CONTROL
*Shared with GPIO
002aaa752
(1) When test/debug interface is used, GPIO/other function sharing these pins are not available. (2) Available in LPC2294 only.
Fig 1. Block diagram.
9397 750 12748 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data
Rev. 01 -- 05 February 2004
RESET
XTAL1
XTAL2
3 of 40
Philips Semiconductors
LPC2292/LPC2294
16/32-bit ARM microcontrollers with external memory interface
5. Pinning information
5.1 Pinning
122 P0.19/MAT1.2/MOSI1/CAP1.2 121 P0.18/CAP1.3/MISO1/MAT1.3 123 P0.20/MAT1.3/SSEL1/EINT3
139 VSSA 138 VSSA_PLL
113 P1.30/TMS
144 P1.27/TDO
126 P1.29/TCK
137 P2.21/D21
136 P2.20/D20
134 P2.19/D19
133 P2.18/D18
132 P2.17/D17
131 P2.16/D16
130 P2.15/D15
129 P2.14/D14
128 VSS 127 P2.13/D13
125 P2.12/D12
124 P2.11/D11
120 P2.10/D10
140 P1.28/TDI
119 V3 118 P2.9/D9
117 P2.8/D8
116 P2.7/D7
115 P2.6/D6
114 P2.5/D5
handbook, full pagewidth
110 V18 109 P2.4/D4
135 RESET
142 XTAL1
141 XTAL2
143 V18A
112 V3 111 VSS
P2.22/D22 V3 VSS P0.21/PWM5/RD3(1)/CAP1.3 P0.22/TD3(1)/CAP0.0/MAT0.0 P0.23/RD2 P1.19/TRACEPKT3 P0.24/TD2 VSS P2.23/D23 P2.24/D24 P2.25/D25 P2.26/D26/BOOT0 V3A P1.18/TRACEPKT2 P2.27/D27/BOOT1 P2.28/D28 P2.29/D29 P2.30/D30/AIN4 P2.31/D31/AIN5 P0.25/RD1 TD1 P0.27/AIN0/CAP0.1/MAT0.1 P1.17/TRACEPKT1 P0.28/AIN1/CAP0.2/MAT0.2 VSS P3.29/BLS2/AIN6 P3.28/BLS3/AIN7 P3.27/WE P3.26/CS1 V3 P0.29/AIN2/CAP0.3/MAT0.3 P0.30/AIN3/EINT3/CAP0.0 P1.16/TRACEPKT0 P3.25/CS2 P3.24/CS3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
108 P2.3/D3 107 VSS 106 P2.2/D2 105 P2.1/D1 104 V3 103 VSS 102 P1.20/TRACESYNC 101 P0.17/CAP1.2/SCK1/MAT1.2 100 P0.16/EINT0/MAT0.2/CAP0.2 99 P0.15/RI1/EINT2 98 P2.0/D0 97 P3.30/BLS1 96 P3.31/BLS0 95 P1.21/PIPESTAT0 94 V3 93 VSS 92 P0.14/DCD1/EINT1
LPC2292/LPC2294
91 P1.0/CS0 90 P1.1/OE 89 P3.0/A0 88 P3.1/A1 87 P3.2/A2 86 P1.22/PIPESTAT1 85 P0.13/DTR1/MAT1.1/TD4(1) 84 P0.12/DSR1/MAT1.0/RD4(1) 83 P0.11/CTS1/CAP1.1 82 P1.23/PIPESTAT2 81 P3.3/A3 80 P3.4/A4 79 VSS 78 P0.10/RTS1/CAP1.0 77 V3 76 P0.9/RxD1/PWM6/EINT3 75 P0.8/TxD1/PWM4 74 P3.5/A5 73 P3.6/A6
002aaa758
P0.1/RxD0/PWM3/EINT0
P0.2/SCL/CAP0.0
P3.23/A23/XCLK
P0.0/TxD0/PWM1
P1.31/TRST
V3 P1.26/RTCK
P0.4/SCK0/CAP0.1
P0.7/SSEL0/PWM2/EINT2
V18 VSS V3
P3.22/A22
P3.21/A21
P3.20/A20
P3.19/A19
P3.18/A18
P3.17/A17
P3.16/A16
VSS P3.15/A15
P3.14/A14
P1.25/EXTIN0
P0.5/MISO0/MAT0.1
P3.13/A13
P3.12/A12
P3.11/A11
P3.10/A10
P3.9/A9
VSS P0.6/MOSI0/CAP0.2
V3 P0.3/SDA/MAT0.0/EINT1
P1.24/TRACECLK
P3.8/A8
(1) Available in LPC2294 only.
Fig 2. LQFP144 pinning.
9397 750 12748
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data
Rev. 01 -- 05 February 2004
P3.7/A7
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Philips Semiconductors
LPC2292/LPC2294
16/32-bit ARM microcontrollers with external memory interface
5.2 Pin description
Table 3: Symbol P0.0 to P0.31 Pin description Pin Type Description Port 0: Port 0 is a 32-bit bi-directional I/O port with individual direction controls for each bit. The operation of port 0 pins depends upon the pin function selected via the Pin Connect Block. Pins 26 and 31 of port 0 are not available. 42, 49, 50, I/O 58, 59, 61, 68, 69, 75, 76, 78, 83-85, 92, 99, 100, 101, 121-123, 4-6, 8, 21, 23, 25, 3, 2, 33 42 49 O O P0.1 I O I P0.2 P0.3 50 58 I/O I I/O O I P0.4 P0.5 59 61 I/O I I/O O P0.6 68 I/O I P0.7 69 I O I P0.8 P0.9 75 76 O O I O I P0.10 78 O I
P0.0
TxD0 -- Transmitter output for UART0. PWM1 -- Pulse Width Modulator output 1. RxD0 -- Receiver input for UART0. PWM3 -- Pulse Width Modulator output 3. EINT0 -- External interrupt 0 input SCL -- I2C clock input/output. Open drain output (for I2C compliance). CAP0.0 -- Capture input for Timer0, channel 0. SDA -- I2C data input/output. Open drain output (for I2C compliance). MAT0.0 -- Match output for Timer0, channel 0. EINT1 -- External interrupt 1 input. SCK0 -- Serial clock for SPI0. SPI clock output from master or input to slave. CAP0.1 -- Capture input for Timer0, channel 1. MISO0 -- Master In Slave OUT for SPI0. Data input to SPI master or data output from SPI slave. MAT0.1 -- Match output for Timer0, channel 1. MOSI0 -- Master Out Slave In for SPI0. Data output from SPI master or data input to SPI slave. CAP0.2 -- Capture input for Timer0, channel 2. SSEL0 -- Slave Select for SPI0. Selects the SPI interface as a slave. PWM2 -- Pulse Width Modulator output 2. EINT2 -- External interrupt 2 input. TxD1 -- Transmitter output for UART1. PWM4 -- Pulse Width Modulator output 4. RxD1 -- Receiver input for UART1. PWM6 -- Pulse Width Modulator output 6. EINT3 -- External interrupt 3 input. RTS1 -- Request to Send output for UART1. CAP1.0 -- Capture input for Timer1, channel 0.
9397 750 12748
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data
Rev. 01 -- 05 February 2004
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Philips Semiconductors
LPC2292/LPC2294
16/32-bit ARM microcontrollers with external memory interface
Table 3: Symbol P0.11 P0.12
Pin description...continued Pin 83 84 Type I I I O I Description CTS1 -- Clear to Send input for UART1. CAP1.1 -- Capture input for Timer1, channel 1. DSR1 -- Data Set Ready input for UART1. MAT1.0 -- Match output for Timer1, channel 0. RD4 -- CAN4 receiver input. DTR1 -- Data Terminal Ready output for UART1. MAT1.1 -- Match output for Timer1, channel 1. TD4 -- CAN4 transmitter output. DCD1 -- Data Carrier Detect input for UART1. EINT1 -- External interrupt 1 input. Note: LOW on this pin while RESET is LOW forces on-chip boot-loader to take over control of the part after reset.
P0.13
85
O O O
P0.14
92
I I
P0.15 P0.16
99 100
I I I O I
RI1 -- Ring Indicator input for UART1. EINT2 -- External interrupt 2 input. EINT0 -- External interrupt 0 input. MAT0.2 -- Match output for Timer0, channel 2. CAP0.2 -- Capture input for Timer0, channel 2. CAP1.2 -- Capture input for Timer1, channel 2. SCK1 -- Serial Clock for SPI1. SPI clock output from master or input to slave. MAT1.2 -- Match output for Timer1, channel 2. CAP1.3 -- Capture input for Timer1, channel 3. MISO1 -- Master In Slave Out for SPI1. Data input to SPI master or data output from SPI slave. MAT1.3 -- Match output for Timer1, channel 3. MAT1.2 -- Match output for Timer1, channel 2. MOSI1 -- Master Out Slave In for SPI1. Data output from SPI master or data input to SPI slave. CAP1.2 -- Capture input for Timer1, channel 2. MAT1.3 -- Match output for Timer1, channel 3. SSEL1 -- Slave Select for SPI1. Selects the SPI interface as a slave. EINT3 -- External interrupt 3 input. PWM5 -- Pulse Width Modulator output 5. RD3 -- CAN3 receiver input. CAP1.3 -- Capture input for TIMER1, channel 3. TD3 -- CAN3 transmitter output. CAP0.0 -- Capture input for Timer0, channel 0. MAT0.0 -- Match output for Timer0, channel 0. RD2 -- CAN2 receiver input. TD2 -- CAN2 transmitter output. RD1 -- CAN1 receiver input.
P0.17
101
I I/O O
P0.18
121
I I/O O
P0.19
122
O I/O I
P0.20
123
O I I
P0.21
4
O I I
P0.22
5
O I O
P0.23 P0.24 P0.25
6 8 21
I O I
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Preliminary data
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LPC2292/LPC2294
16/32-bit ARM microcontrollers with external memory interface
Table 3: Symbol P0.27
Pin description...continued Pin 23 Type I I O Description AIN0 -- A/D converter, input 0. This analog input is always connected to its pin. CAP0.1 -- Capture input for Timer0, channel 1. MAT0.1 -- Match output for Timer0, channel 1. AIN1 -- A/D converter, input 1. This analog input is always connected to its pin. CAP0.2 -- Capture input for Timer0, channel 2. MAT0.2 -- Match output for Timer0, channel 2. AIN2 -- A/D converter, input 2. This analog input is always connected to its pin. CAP0.3 -- Capture input for Timer0, Channel 3. MAT0.3 -- Match output for Timer0, channel 3. AIN3 -- A/D converter, input 3. This analog input is always connected to its pin. EINT3 -- External interrupt 3 input. CAP0.0 -- Capture input for Timer0, channel 0. Port 1: Port 1 is a 32-bit bi-directional I/O port with individual direction controls for each bit. The operation of port 1 pins depends upon the pin function selected via the Pin Connect Block. Pins 2 through 15 of port 1 are not available.
P0.28
25
I I O
P0.29
32
I I O
P0.30
33
I I I
P1.0 to P1.31
91, 90, 34, I/O 24, 15, 7, 102, 95, 86, 82, 70, 60, 52, 144, 140, 126, 113, 43 91 90 34 24 15 7 102 O O O O O O O
P1.0 P1.1 P1.16 P1.17 P1.18 P1.19 P1.20
CS0 -- Low-active Chip Select 0 signal. (Bank 0 addresses range 8000 0000 - 80FF FFFF) OE -- Low-active Output Enable signal. TRACEPKT0 -- Trace Packet, bit 0. Standard I/O port with internal pull-up. TRACEPKT1 -- Trace Packet, bit 1. Standard I/O port with internal pull-up. TRACEPKT2 -- Trace Packet, bit 2. Standard I/O port with internal pull-up. TRACEPKT3 -- Trace Packet, bit 3. Standard I/O port with internal pull-up. TRACESYNC -- Trace Synchronization. Standard I/O port with internal pull-up. Note: LOW on this pin while RESET is LOW, enables pins P1.25:16 to operate as Trace port after reset.
P1.21 P1.22 P1.23 P1.24 P1.25 P1.26
95 86 82 70 60 52
O O O O I I/O
PIPESTAT0 -- Pipeline Status, bit 0. Standard I/O port with internal pull-up. PIPESTAT1 -- Pipeline Status, bit 1. Standard I/O port with internal pull-up. PIPESTAT2 -- Pipeline Status, bit 2. Standard I/O port with internal pull-up. TRACECLK -- Trace Clock. Standard I/O port with internal pull-up. EXTIN0 -- External Trigger Input. Standard I/O with internal pull-up. RTCK -- Returned Test Clock output. Extra signal added to the JTAG port. Assists debugger synchronization when processor frequency varies. Bi-directional pin with internal pull-up. Note: LOW on this pin while RESET is LOW, enables pins P1.31:26 to operate as Debug port after reset.
P1.27
9397 750 12748
144
O
TDO -- Test Data out for JTAG interface.
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Preliminary data
Rev. 01 -- 05 February 2004
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Philips Semiconductors
LPC2292/LPC2294
16/32-bit ARM microcontrollers with external memory interface
Table 3: Symbol P1.28 P1.29 P1.30 P1.31
Pin description...continued Pin 140 126 113 43 Type I I I I Description TDI -- Test Data in for JTAG interface. TCK -- Test Clock for JTAG interface. TMS -- Test Mode Select for JTAG interface. TRST -- Test Reset for JTAG interface. Port 2 -- Port 2 is a 32-bit bi-directional I/O port with individual direction controls for each bit. The operation of port 2 pins depends upon the pin function selected via the Pin Connect Block.
P2.0 to P2.31
98, 105, 106, I/O 108, 109, 114-118, 120, 124, 125, 127, 129-134, 136, 137, 1, 10-13, 16-20 98 105 106 108 109 114 115 116 117 118 120 124 125 127 129 130 131 132 133 134 136 137 1 10 11 12 13 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I
P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P2.8 P2.9 P2.10 P2.11 P2.12 P2.13 P2.14 P2.15 P2.16 P2.17 P2.18 P2.19 P2.20 P2.21 P2.22 P2.23 P2.24 P2.25 P2.26
D0 -- External memory data line 0. D1 -- External memory data line 1. D2 -- External memory data line 2. D3 -- External memory data line 3. D4 -- External memory data line 4. D5 -- External memory data line 5. D6 -- External memory data line 6. D7 -- External memory data line 7. D8 -- External memory data line 8. D9 -- External memory data line 9. D10 -- External memory data line 10. D11 -- External memory data line 11. D12 -- External memory data line 12. D13 -- External memory data line 13. D14 -- External memory data line 14. D15 -- External memory data line 15. D16 -- External memory data line 16. D17 -- External memory data line 17. D18 -- External memory data line 18. D19 -- External memory data line 19. D20 -- External memory data line 20. D21 -- External memory data line 21. D22 -- External memory data line 22. D23 -- External memory data line 23. D24 -- External memory data line 24. D25 -- External memory data line 25. D26 -- External memory data line 26. BOOT0 -- While RESET is low, together with BOOT1 controls booting and internal operation. Internal pull-up ensures high state if pin is left unconnected.
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LPC2292/LPC2294
16/32-bit ARM microcontrollers with external memory interface
Table 3: Symbol P2.27
Pin description...continued Pin 16 Type I/O I Description D27 -- External memory data line 27. BOOT1 -- While RESET is low, together with BOOT0 controls booting and internal operation. Internal pull-up ensures high state if pin is left unconnected. BOOT1:0=00 selects 8-bit memory on CS0 for boot. BOOT1:0=01 selects 16-bit memory on CS0 for boot. BOOT1:0=10 selects 32-bit memory on CS0 for boot. BOOT1:0=11 selects Internal Flash memory.
P2.28 P2.29 P2.30
17 18 19
I/O I/O I/O I
D28 -- External memory data line 28. D29 -- External memory data line 29. D30 -- External memory data line 30. AIN4 -- A/D converter, input 4. This analog input is always connected to its pin. D31 -- External memory data line 31. AIN5 -- A/D converter, input 5. This analog input is always connected to its pin. Port 3 -- Port 3 is a 32-bit bi-directional I/O port with individual direction controls for each bit. The operation of port 3 pins depends upon the pin function selected via the Pin Connect Block.
P2.31
20
I/O I
P3.0 to P3.31
89-87, 81, I/O 80, 74-71, 66-62, 56, 55, 53, 48-44, 41, 40, 36, 35, 30-27, 97, 96 89 88 87 81 80 74 73 72 71 66 65 64 63 62 56 55 53 48 47 46 O O O O O O O O O O O O O O O O O O O O
P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P3.8 P3.9 P3.10 P3.11 P3.12 P3.13 P3.14 P3.15 P3.16 P3.17 P3.18 P3.19
9397 750 12748
A0 -- External memory address line 0. A1 -- External memory address line 1. A2 -- External memory address line 2. A3 -- External memory address line 3. A4 -- External memory address line 4. A5 -- External memory address line 5. A6 -- External memory address line 6. A7 -- External memory address line 7. A8 -- External memory address line 8. A9 -- External memory address line 9. A10 -- External memory address line 10. A11 -- External memory address line 11. A12 -- External memory address line 12. A13 -- External memory address line 13. A14 -- External memory address line 14. A15 -- External memory address line 15. A16 -- External memory address line 16. A17 -- External memory address line 17. A18 -- External memory address line 18. A19 -- External memory address line 19.
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data
Rev. 01 -- 05 February 2004
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Philips Semiconductors
LPC2292/LPC2294
16/32-bit ARM microcontrollers with external memory interface
Table 3: Symbol P3.20 P3.21 P3.22 P3.23 P3.24 P3.25 P3.26 P3.27 P3.28
Pin description...continued Pin 45 44 41 40 36 35 30 29 28 Type O O O I/O O O O O O O I Description A20 -- External memory address line 20. A21 -- External memory address line 21. A22 -- External memory address line 22. A23 -- External memory address line 23. XCLK -- Clock output. CS3 -- Low-active Chip Select 3 signal. (Bank 3 addresses range 8300 0000 - 83FF FFFF) CS2 -- Low-active Chip Select 2signal. (Bank 2 addresses range 8200 0000 - 82FF FFFF) CS1 -- Low-active Chip Select 1 signal. (Bank 1 addresses range 8100 0000 - 81FF FFFF) WE -- Low-active Write enable signal. BLS3 -- Low-active Byte Lane Select signal (Bank 3). AIN7 -- A/D converter, input 7. This analog input is always connected to its pin. BLS2 -- Low-active Byte Lane Select signal (Bank 2). AIN6 -- A/D converter, input 6. This analog input is always connected to its pin. BLS1 -- Low-active Byte Lane Select signal (Bank 1). BLS0 -- Low-active Byte Lane Select signal (Bank 0). TD1: CAN1 transmitter output. External Reset input: A LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. TTL with hysteresis, 5 V tolerant. Input to the oscillator circuit and internal clock generator circuits. Output from the oscillator amplifier. Ground: 0 V reference.
P3.29
27
O I
P3.30 P3.31 TD1 RESET
97 96 22 135
O O O I
XTAL1 XTAL2 VSS
142 141
I O
3, 9, 26, 38, I 54, 67, 79, 93, 103, 107, 111, 128 139 138 37, 110 143 I I I I
VSSA VSSA_PLL V18 V18A
Analog Ground: 0 V reference. This should nominally be the same voltage as VSS, but should be isolated to minimize noise and error. PLL Analog Ground: 0 V reference. This should nominally be the same voltage as VSS, but should be isolated to minimize noise and error. 1.8 V Core Power Supply: This is the power supply voltage for internal circuitry. Analog 1.8 V Core Power Supply: This is the power supply voltage for internal circuitry. This should be nominally the same voltage as V18 but should be isolated to minimize noise and error. 3.3 V Pad Power Supply: This is the power supply voltage for the I/O ports.
V3
2, 31, 39, 51, I 57, 77, 94, 104, 112, 119 14 I
V3A
Analog 3.3 V Pad Power Supply: This should be nominally the same voltage as V3 but should be isolated to minimize noise and error.
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 12748
Preliminary data
Rev. 01 -- 05 February 2004
10 of 40
Philips Semiconductors
LPC2292/LPC2294
16/32-bit ARM microcontrollers with external memory interface
6. Functional description
Details of the LPC2292/LPC2294 systems and peripheral functions are described in the following sections.
6.1 Architectural overview
The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed Complex Instruction Set Computers. This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor core. Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. The ARM7TDMI-S processor also employs a unique architectural strategy known as THUMB, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue. The key idea behind THUMB is that of a super-reduced instruction set. Essentially, the ARM7TDMI-S processor has two instruction sets:
* The standard 32-bit ARM set. * A 16-bit THUMB set.
The THUMB set's 16-bit instruction length allows it to approach twice the density of standard ARM code while retaining most of the ARM's performance advantage over a traditional 16-bit processor using 16-bit registers. This is possible because THUMB code operates on the same 32-bit register set as ARM code. THUMB code is able to provide up to 65% of the code size of ARM, and 160% of the performance of an equivalent ARM processor connected to a 16-bit memory system.
6.2 On-Chip Flash program memory
The LPC2292/LPC2294 incorporate a 256 kB Flash memory system respectively. This memory may be used for both code and data storage. Programming of the Flash memory may be accomplished in several ways. It may be programmed In System via the serial port. The application program may also erase and/or program the Flash while the application is running, allowing a great degree of flexibility for data storage field firmware upgrades, etc. When on-chip bootloader is used, 248 kB of Flash memory is available for user code.
6.3 On-Chip static RAM
On-Chip static RAM may be used for code and/or data storage. The SRAM may be accessed as 8-bits, 16-bits, and 32-bits. The LPC2292/LPC2294 provide 16 kB of static RAM.
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LPC2292/LPC2294
16/32-bit ARM microcontrollers with external memory interface
6.4 Memory map
The LPC2292/LPC2294 memory maps incorporate several distinct regions, as shown in the following figures. In addition, the CPU interrupt vectors may be re-mapped to allow them to reside in either Flash memory (the default) or on-chip static RAM. This is described in Section 6.21 "System control".
4.0 GB AHB PERIPHERALS 3.75 GB VPB PERIPHERALS 3.5 GB
0xFFFF FFFF 0xF000 0000 0xEFFF FFFF 0xE000 0000 0xDFFF FFFF
3.0 GB RESERVED ADDRESS SPACE
0xC000 0000
2.0 GB
BOOT BLOCK (RE-MAPPED FROM ON-CHIP FLASH MEMORY
0x8000 0000 0x7FFF FFFF 0x7FFF E000 0x7FFF DFFF
RESERVED ADDRESS SPACE 0x4001 0000 0x4000 3FFF 16 KBYTE ON-CHIP STATIC RAM 1.0 GB 0x4000 0000 0x3FFF FFFF
RESERVED ADDRESS SPACE
0x0004 0000 0x0003 FFFF 256 KBYTE ON-CHIP FLASH MEMORY 0.0 GB 0x0000 0000
002aaa754
Fig 3. LPC2292/LPC2294 memory map.
6.5 Interrupt controller
The Vectored Interrupt Controller (VIC) accepts all of the interrupt request inputs and categorizes them as FIQ, vectored IRQ, and non-vectored IRQ as defined by programmable settings. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted.
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16/32-bit ARM microcontrollers with external memory interface
Fast Interrupt reQuest (FIQ) has the highest priority. If more than one request is assigned to FIQ, the VIC combines the requests to produce the FIQ signal to the ARM processor. The fastest possible FIQ latency is achieved when only one request is classified as FIQ, because then the FIQ service routine can simply start dealing with that device. But if more than one request is assigned to the FIQ class, the FIQ service routine can read a word from the VIC that identifies which FIQ source(s) is (are) requesting an interrupt. Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be assigned to this category. Any of the interrupt requests can be assigned to any of the 16 vectored IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest. Non-vectored IRQs have the lowest priority. The VIC combines the requests from all the vectored and non-vectored IRQs to produce the IRQ signal to the ARM processor. The IRQ service routine can start by reading a register from the VIC and jumping there. If any of the vectored IRQs are requesting, the VIC provides the address of the highest-priority requesting IRQs service routine, otherwise it provides the address of a default routine that is shared by all the non-vectored IRQs. The default routine can read another VIC register to see what IRQs are active. 6.5.1 Interrupt sources Table 4 lists the interrupt sources for each peripheral function. Each peripheral device has one interrupt line connected to the Vectored Interrupt Controller, but may have several internal interrupt flags. Individual interrupt flags may also represent more than one interrupt source.
Table 4: Block WDT ARM Core ARM Core Timer0 Timer1 UART0 Interrupt sources Flag(s) Watchdog Interrupt (WDINT) Reserved for software interrupts only Embedded ICE, DbgCommRx Embedded ICE, DbgCommTx Match 0 - 3 (MR0, MR1, MR2, MR3) Capture 0 - 3 (CR0, CR1, CR2, CR3) Match 0 - 3 (MR0, MR1, MR2, MR3) Capture 0 - 3 (CR0, CR1, CR2, CR3) Rx Line Status (RLS) Transmit Holding Register empty (THRE) Rx Data Available (RDA) Character Time-out Indicator (CTI) UART1 Rx Line Status (RLS) Transmit Holding Register empty (THRE) Rx Data Available (RDA) Character Time-out Indicator (CTI) Modem Status Interrupt (MSI) PWM0
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VIC channel # 0 1 2 3 4 5 6
7
Match 0 - 6 (MR0, MR1, MR2, MR3, MR4, MR5, MR6)
8
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16/32-bit ARM microcontrollers with external memory interface
Interrupt sources...continued Flag(s) SI (state change) SPIF, MODF SPIF, MODF PLL Lock (PLOCK) RTCCIF (Counter Increment), RTCALF (Alarm) External Interrupt 1 (EINT1) External Interrupt 2 (EINT2) External Interrupt 3 (EINT3) VIC channel # 9 10 11 12 13 14 15 16 17 18 19 20,21 22,23 24,25 26,27
Table 4: Block I2C SPI0 SPI1 PLL RTC
System Control External Interrupt 0 (EINT0)
A/D CAN
A/D Converter 1 ORed CAN Acceptance Filter CAN1 (Tx int, Rx int) CAN2 (Tx int, Rx int) CAN3 (Tx int, Rx int) - LPC2294 only CAN4 (Tx int, Rx int) - LPC2294 only
6.6 Pin connect block
The pin connect block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on chip peripherals. Peripherals should be connected to the appropriate pins prior to being activated, and prior to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined. The Pin Control Module contains three registers as shown in Table 5.
Table 5: Address 0xE002C000 0xE002C004 0xE002C014 Name PINSEL0 PINSEL1 PINSEL2 Description Pin function select register 0 Pin function select register 1 Pin function select register 2 Access Read/Write Read/Write Read/Write
6.7 Pin function select register 0 (PINSEL0 - 0xE002C000)
The PINSEL0 register controls the functions of the pins as per the settings listed in Table 6. The direction control bit in the IODIR register is effective only when the GPIO function is selected for a pin. For other functions, direction is controlled automatically. Settings other than those shown in Table 6 are reserved, and should not be used
Table 6: PINSEL0 1:0 Pin function select register 0 (PINSEL0 - 0xE002C000) Pin name P0.0 Value 0 0 1 1
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Function 0 1 0 1 GPIO Port 0.0 TxD (UART0) PWM1 Reserved
Value after Reset 0
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16/32-bit ARM microcontrollers with external memory interface
Pin function select register 0 (PINSEL0 - 0xE002C000)...continued Pin name P0.1 Value 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function GPIO Port 0.1 RxD (UART0) PWM3 EINT0 GPIO Port 0.2 SCL (I2C) Capture 0.0 (Timer0) Reserved GPIO Port 0.3 SDA (I2C) Match 0.0 (Timer0) EINT1 GPIO Port 0.4 SCK (SPI0) Capture 0.1 (Timer0) Reserved GPIO Port 0.5 MISO (SPI0) Match 0.1 (Timer0) Reserved GPIO Port 0.6 MOSI (SPI0) Capture 0.2 (Timer0) Reserved GPIO Port 0.7 SSEL (SPI0) PWM2 EINT2 GPIO Port 0.8 TxD UART1 PWM4 Reserved GPIO Port 0.9 RxD (UART1) PWM6 EINT3 GPIO Port 0.10 RTS (UART1) Capture 1.0 (Timer1) Reserved 0 0 0 0 0 0 0 0 0 Value after Reset 0
Table 6: PINSEL0 3:2
5:4
P0.2
0 0 1 1
7:6
P0.3
0 0 1 1
9:8
P0.4
0 0 1 1
11:10
P0.5
0 0 1 1
13:12
P0.6
0 0 1 1
15:14
P0.7
0 0 1 1
17:16
P0.8
0 0 1 1
19:18
P0.9
0 0 1 1
21:20
P0.10
0 0 1 1
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16/32-bit ARM microcontrollers with external memory interface
Pin function select register 0 (PINSEL0 - 0xE002C000)...continued Pin name P0.11 Value 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function GPIO Port 0.11 CTS (UART1) Capture 1.1 (Timer1) Reserved GPIO Port 0.12 DSR (UART1) Match 1.0 (Timer1) RD4[1] (CAN Controller 4) GPIO Port 0.13 DTR (UART1) Match 1.1 (Timer1) TD4[1] (CAN Controller 4) GPIO Port 0.14 DCD (UART1) EINT1 Reserved GPIO Port 0.15 RI (UART1) EINT2 Reserved 0 0 0 0 Value after Reset 0
Table 6: PINSEL0 23:22
25:24
P0.12
0 0 1 1
27:26
P0.13
0 0 1 1
29:28
P0.14
0 0 1 1
31:30
P0.15
0 0 1 1
[1]
CAN Controller 4 is available in LPC2294 only. Fields in the table related to CAN4 have Reserved value for LPC2292.
6.8 Pin function select register 1 (PINSEL1 - 0xE002C004)
The PINSEL1 register controls the functions of the pins as per the settings listed in Table 7. The direction control bit in the IODIR register is effective only when the GPIO function is selected for a pin. For other functions direction is controlled automatically. Settings other than those shown in the table are reserved, and should not be used.
Table 7: PINSEL1 1:0 Pin function select register 1 (PINSEL1 - 0xE002C004) Pin Name P0.16 Value 0 0 1 1 3:2 P0.17 0 0 1 1 0 1 0 1 0 1 0 1 Function GPIO Port 0.16 EINT0 Match 0.2 (Timer0) Reserved GPIO Port 0.17 Capture 1.2 (Timer1) SCK (SPI1) Match 1.2 (Timer1) 0 Value after Reset 0
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16/32-bit ARM microcontrollers with external memory interface
Pin function select register 1 (PINSEL1 - 0xE002C004)...continued Pin Name P0.18 Value 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function GPIO Port 0.18 Capture 1.3 (Timer1) MISO (SPI1) Match 1.3 (Timer1) GPIO Port 0.19 Match 1.2 (Timer1) MOSI (SPI1) Match 1.3 (Timer1) GPIO Port 0.20 Match 1.3 (Timer1) SSEL (SPI1) EINT3 GPIO Port 0.21 PWM5 RD3[1] (CAN Controller 3) Capture 1.3 (Timer1) GPIO Port 0.22 TD3[1] (CAN Controller 3) Capture 0.0 (Timer0) Match 0.0 (Timer0) GPIO Port 0.23 RD2 (CAN Controller 2) Reserved Reserved GPIO Port 0.24 TD2 (CAN Controller 2) Reserved Reserved GPIO Port 0.25 RD1 (CAN Controller 1) Reserved Reserved Reserved Reserved Reserved Reserved GPIO Port 0.27 AIN0 (A/D converter) Capture 0.1 (Timer0) Match 0.1 (Timer0)
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Table 7: PINSEL1 5:4
Value after Reset 0
7:6
P0.19
0 0 1 1
0
9:8
P0.20
0 0 1 1
0
11:10
P0.21
0 0 1 1
0
13:12
P0.22
0 0 1 1
0
15:14
P0.23
0 0 1 1
0
17:16
P0.24
0 0 1 1
0
19:18
P0.25
0 0 1 1
0
21:20
P0.26
0 0 1 1
0
23:22
P0.27
0 0 1 1
1
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LPC2292/LPC2294
16/32-bit ARM microcontrollers with external memory interface
Pin function select register 1 (PINSEL1 - 0xE002C004)...continued Pin Name P0.28 Value 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function GPIO Port 0.28 AIN1 (A/D converter) Capture 0.2 (Timer0) Match 0.2 (Timer0) GPIO Port 0.29 AIN2 (A/D converter) Capture 0.3 (Timer0) Match 0.3 (Timer0) GPIO Port 0.30 AIN3 (A/D converter) EINT3 Capture 0.0 (Timer0) Reserved Reserved Reserved Reserved 0 1 1 Value after Reset 1
Table 7: PINSEL1 25:24
27:26
P0.29
0 0 1 1
29:28
P0.30
0 0 1 1
31:30
P0.31
0 0 1 1
[1]
CAN Controller 3 is available in LPC2294 only. Fields in the table related to CAN3 have Reserved value for LPC2292.
6.9 Pin function select register 2 (PINSEL2 - 0xE002C014)
The PINSEL2 register controls the functions of the pins as per the settings listed in Table 8. The direction control bit in the IODIR register is effective only when the GPIO function is selected for a pin. For other functions direction is controlled automatically. Settings other than those shown in the table are reserved, and should not be used.
Table 8: 1:0 2 3 Pin function select register 2 (PINSEL2 - 0xE002C014) Description Reserved. When 0, pins P1.36:26 are used as GPIO pins. When 1, P1.31:26 are used as a Debug port. When 0, pins P1.25:16 are used as GPIO pins. When 1, P1.25:16 are used as a Trace port. Reset value P1.26/RTCK P1.20/ TRACESYNC
PINSEL2 bits
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16/32-bit ARM microcontrollers with external memory interface
Table 8: 5:4
Pin function select register 2 (PINSEL2 - 0xE002C014)...continued Description Controls the use of the data bus and strobe pins: Pins P2.7:0 Pin P1.0 Pin P1.1 Pin P3.31 Pins P2.15:8 Pin P3.30 Pins P2.27:16 Pins P2.29:28 Pins P2.31:30 Pins P3.29:28 11 = P2.7:0 11 = P1.0 11 = P1.1 11 = P3.31 00 or 11 = P2.15:8 00 or 11 = P3.30 0x or 11 = P2.27:16 0x or 11 = P2.29:28 or reserved 0x or 11 = P2.31:30 or AIN5:4 0x or 11 = P3.29:28 or AIN6:7 0x or 10 = D7:0 0x or 10 = CS0 0x or 10 = OE 0x or 10 = BLS0 01 or 10 = D15:8 01 or 10 = BLS1 10 = D27:16 10 = D29:28 10 = D31:30 10 = BLS2:3 1 1 0 0 Reset value BOOT1:0
PINSEL2 bits
6 7 8 10:9 11 12 13 15:14 17:16 19:18 20 21 22 23
If bits 5:4 are not 10, controls the use of pin P3.29: 0 enables P3.29, 1 enables AIN6. If bits 5:4 are not 10, controls the use of pin P3.28: 0 enables P3.28, 1 enables AIN7. Controls the use of pin P3.27: 0 enables P3.27, 1 enables WE. Reserved. Controls the use of pin P3.26: 0 enables P3.26, 1 enables CS1. Reserved.
If bits 25:23 are not 111, controls the use of pin P3.23/A23/XCLK: 0 enables P3.23, 0 1 enables XCLK. Controls the use of pin P3.25: 00 enables P3.25, 01 enables CS2, 10 and 11 are reserved values. Controls the use of pin P3.24: 00 enables P3.24, 01 enables CS3, 10 and 11 are reserved values. Reserved. If bits 5:4 are not 10, controls the use of pin P2.29:28: 0 enables P2.29:28, 1 is reserved If bits 5:4 are not 10, controls the use of pin P2.30: 0 enables P2.30, 1 enables AIN4. If bits 5:4 are not 10, controls the use of pin P2.31: 0 enables P2.31, 1 enables AIN5. Controls whether P3.0/A0 is a port pin (0) or an address line (1). 00 00 0 1 1 1 if BOOT1:0=00 at RESET=0, 0 otherwise BOOT1 during Reset
24 27:25
Controls whether P3.1/A1 is a port pin (0) or an address line (1).
Controls the number of pins among P3.23/A23/XCLK and P3.22:2/A2.22:2 that are 000 if BOOT1:0=11 address lines: at Reset, 111 otherwise 000 = None 100 = A11:2 are address lines. 001 = A3:2 are address lines. 010 = A5:2 are address lines. 011 = A7:2 are address lines. 101 = A15:2 are address lines. 110 = A19:2 are address lines. 111 = A23:2 are address lines.
31:28
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Reserved.
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16/32-bit ARM microcontrollers with external memory interface
6.10 External memory controller
The external Static Memory Controller is a module which provides an interface between the system bus and external (off-chip) memory devices. It provides support for up to four independently configurable memory banks (16 MBytes each with byte lane enable control) simultaneously. Each memory banks is capable of supporting SRAM, ROM, Flash EPROM, Burst ROM memory, or some external I/O devices. Each memory bank may be 8, 16, or 32 bits wide.
6.11 General purpose parallel I/O
Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate registers allow setting or clearing any number of outputs simultaneously. The value of the output register may be read back, as well as the current state of the port pins. 6.11.1 Features
* Direction control of individual bits. * Separate control of output set and clear. * All I/O default to inputs after reset. 6.12 10-bit A/D converter
The LPC2292/LPC2294 each contain single 10-bit successive approximation analog to digital converter with eight multiplexed channels. 6.12.1 Features
* * * *
Measurement range of 0 V to 3 V. Capable of performing more than 400,000 10-bit samples per second. Burst conversion mode for single or multiple inputs. Optional conversion on transition on input pin or Timer Match signal.
6.13 CAN controllers and acceptance filter
The LPC2292/LPC2294 each contain two/four CAN controllers. The Controller Area network (CAN) is a serial communications protocol which efficiently supports distributed real-time control with a very high level of security. Its domain of application ranges from high speed networks to low cost multiplex wiring. 6.13.1 Features
* * * * *
Data rates up to 1 Mbit/s on each bus. 32-bit register and RAM access. Compatible with CAN specification 2.0B, ISO 11898-1. Global Acceptance Filter recognizes 11 and 29-bit Rx identifiers for all CAN buses. Acceptance Filter can provide FullCAN-style automatic reception for selected Standard identifiers.
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LPC2292/LPC2294
16/32-bit ARM microcontrollers with external memory interface
6.14 UARTs
The LPC2292/LPC2294 each contain two UARTs. One UART provides a full modem control handshake interface, the other provides only transmit and receive data lines. 6.14.1 Features
* * * * *
16 byte Receive and Transmit FIFOs. Register locations conform to `550 industry standard. Receiver FIFO trigger points at 1, 4, 8, and 14 bytes Built-in baud rate generator. Standard modem interface signals included on UART1.
6.15 I2C serial I/O controller
I2C is a bi-directional bus for inter-IC control using only two wires: a serial clock line (SCL), and a serial data line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g. an LCD driver or a transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. I2C is a multi-master bus, it can be controlled by more than one bus master connected to it. I2C implemented in LPC2292/LPC2294 supports bit rate up to 400 kbit/s (Fast I2C). 6.15.1 Features
* Standard I2C compliant bus interface. * Easy to configure as Master, Slave, or Master/Slave. * Programmable clocks allow versatile rate control. * Bidirectional data transfer between masters and slaves. * Multi-master bus (no central master). * Arbitration between simultaneously transmitting masters without corruption of
serial data on the bus.
* Serial clock synchronization allows devices with different bit rates to communicate
via one serial bus.
* Serial clock synchronization can be used as a handshake mechanism to suspend
and resume serial transfer.
* The I2C bus may be used for test and diagnostic purposes. 6.16 SPI serial I/O controller
The LPC2292/LPC2294 each contain two SPIs. The SPI is a full duplex serial interface, designed to be able to handle multiple masters and slaves connected to a given bus. Only a single master and a single slave can communicate on the interface during a given data transfer. During a data transfer the master always sends a byte of data to the slave, and the slave always sends a byte of data to the master.
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16/32-bit ARM microcontrollers with external memory interface
6.16.1
Features
* Compliant with Serial Peripheral Interface (SPI) specification. * Synchronous, Serial, Full Duplex, Communication. * Combined SPI master and slave. * Maximum data bit rate of one eighth of the input clock rate. 6.17 General purpose timers
The Timer is designed to count cycles of the peripheral clock (PCLK) and optionally generate interrupts or perform other actions at specified timer values, based on four match registers. It also includes four capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. Multiple pins can be selected to perform a single capture or match function, providing an application with `or' and `and', as well as `broadcast' functions among them. 6.17.1 Features
* A 32-bit Timer/Counter with a programmable 32-bit Prescaler. * Four 32-bit capture channels per timer that can take a snapshot of the timer value
when an input signal transitions. A capture event may also optionally generate an interrupt.
* Four 32-bit match registers that allow:
- Continuous operation with optional interrupt generation on match. - Stop timer on match with optional interrupt generation. - Reset timer on match with optional interrupt generation.
* Four external outputs per timer corresponding to match registers, with the following
capabilities: - Set LOW on match. - Set HIGH on match. - Toggle on match. - Do nothing on match.
6.18 Watchdog timer
The purpose of the Watchdog is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state. When enabled, the Watchdog will generate a system reset if the user program fails to `feed' (or reload) the Watchdog within a predetermined amount of time. 6.18.1 Features
* Internally resets chip if not periodically reloaded. * Debug mode.
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16/32-bit ARM microcontrollers with external memory interface
* Enabled by software but requires a hardware reset or a Watchdog reset/interrupt to
be disabled.
* Incorrect/Incomplete feed sequence causes reset/interrupt if enabled. * Flag to indicate Watchdog reset. * Programmable 32-bit timer with internal pre-scaler. * Selectable time period from (tpclk x 256 x 4) to (tpclk x 232 x 4) in multiples of
tpclk x 4.
6.19 Real time clock
The Real Time Clock (RTC) is designed to provide a set of counters to measure time when normal or idle operating mode is selected. The RTC has been designed to use little power, making it suitable for battery powered systems where the CPU is not running continuously (Idle mode). 6.19.1 Features
* Measures the passage of time to maintain a calendar and clock. * Ultra Low Power design to support battery powered systems. * Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and
Day of Year.
* Programmable Reference Clock Divider allows adjustment of the RTC to match
various crystal frequencies.
6.20 Pulse width modulator
The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC2292/LPC2294. The Timer is designed to count cycles of the peripheral clock (PCLK) and optionally generate interrupts or perform other actions when specified timer values occur, based on seven match registers. The PWM function is also based on match register events. The ability to separately control rising and falling edge locations allows the PWM to be used for more applications. For instance, multi-phase motor control typically requires three non-overlapping PWM outputs with individual control of all three pulse widths and positions. Two match registers can be used to provide a single edge controlled PWM output. One match register (MR0) controls the PWM cycle rate, by resetting the count upon match. The other match register controls the PWM edge position. Additional single edge controlled PWM outputs require only one match register each, since the repetition rate is the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a rising edge at the beginning of each PWM cycle, when an MR0 match occurs.
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16/32-bit ARM microcontrollers with external memory interface
Three match registers can be used to provide a PWM output with both edges controlled. Again, the MR0 match register controls the PWM cycle rate. The other match registers control the two PWM edge positions. Additional double edge controlled PWM outputs require only two match registers each, since the repetition rate is the same for all PWM outputs. With double edge controlled PWM outputs, specific match registers control the rising and falling edge of the output. This allows both positive going PWM pulses (when the rising edge occurs prior to the falling edge), and negative going PWM pulses (when the falling edge occurs prior to the rising edge). 6.20.1 Features
* Seven match registers allow up to six single edge controlled or three double edge
controlled PWM outputs, or a mix of both types.
* The match registers also allow:
- Continuous operation with optional interrupt generation on match. - Stop timer on match with optional interrupt generation. - Reset timer on match with optional interrupt generation.
* Supports single edge controlled and/or double edge controlled PWM outputs.
Single edge controlled PWM outputs all go HIGH at the beginning of each cycle unless the output is a constant LOW. Double edge controlled PWM outputs can have either edge occur at any position within a cycle. This allows for both positive going and negative going pulses.
* Pulse period and width can be any number of timer counts. This allows complete
flexibility in the trade-off between resolution and repetition rate. All PWM outputs will occur at the same repetition rate.
* Double edge controlled PWM outputs can be programmed to be either positive
going or negative going pulses.
* Match register updates are synchronized with pulse outputs to prevent generation
of erroneous pulses. Software must `release' new match values before they can become effective.
* May be used as a standard timer if the PWM mode is not enabled. * A 32-bit Timer/Counter with a programmable 32-bit Prescaler. 6.21 System control
6.21.1 Crystal oscillator The oscillator supports crystals in the range of 1 MHz to 30 MHz. The oscillator output frequency is called fosc and the ARM processor clock frequency is referred to as cclk for purposes of rate equations, etc. fosc and cclk are the same value unless the PLL is running and connected. Refer to Section 6.21.2 "PLL" for additional information.
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16/32-bit ARM microcontrollers with external memory interface
6.21.2
PLL The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input frequency is multiplied up into the range of 10 MHz to 60 MHz with a Current Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the multiplier value cannot be higher than 6 on this family of microcontrollers due to the upper frequency limit of the CPU). The CCO operates in the range of 156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within its frequency range while the PLL is providing the desired output frequency. The output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2, it is insured that the PLL output has a 50% duty cycle.The PLL is turned off and bypassed following a chip Reset and may be enabled by software. The program must configure and activate the PLL, wait for the PLL to Lock, then connect to the PLL as a clock source.
6.21.3
Reset and wake-up timer Reset has two sources on the LPC2292/LPC2294: the RESET pin and Watchdog Reset. The RESET pin is a Schmitt trigger input pin with an additional glitch filter. Assertion of chip Reset by any source starts the Wake-up Timer (see Wake-up Timer description below), causing the internal chip reset to remain asserted until the external Reset is de-asserted, the oscillator is running, a fixed number of clocks have passed, and the on-chip Flash controller has completed its initialization. When the internal Reset is removed, the processor begins executing at address 0, which is the Reset vector. At that point, all of the processor and peripheral registers have been initialized to predetermined values. The wake-up timer ensures that the oscillator and other analog functions required for chip operation are fully functional before the processor is allowed to execute instructions. This is important at power on, all types of Reset, and whenever any of the aforementioned functions are turned off for any reason. Since the oscillator and other functions are turned off during Power-down mode, any wake-up of the processor from Power-down mode makes use of the Wake-up Timer. The Wake-up Timer monitors the crystal oscillator as the means of checking whether it is safe to begin code execution. When power is applied to the chip, or some event caused the chip to exit Power-down mode, some time is required for the oscillator to produce a signal of sufficient amplitude to drive the clock logic. The amount of time depends on many factors, including the rate of VDD ramp (in the case of power on), the type of crystal and its electrical characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the existing ambient conditions.
6.21.4
External interrupt inputs The LPC2292/LPC2294 include up to nine edge or level sensitive External Interrupt Inputs as selectable pin functions. When the pins are combined, external events can be processed as four independent interrupt signals. The External Interrupt Inputs can optionally be used to wake up the processor from Power-down mode.
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16/32-bit ARM microcontrollers with external memory interface
6.21.5
Memory Mapping Control The Memory Mapping Control alters the mapping of the interrupt vectors that appear beginning at address 0x00000000. Vectors may be mapped to the bottom of the on-chip Flash memory, or to the on-chip static RAM. This allows code running in different memory spaces to have control of the interrupts.
6.21.6
Power Control The LPC2292/LPC2294 support two reduced power modes: Idle mode and Power-down mode. In Idle mode, execution of instructions is suspended until either a Reset or interrupt occurs. Peripheral functions continue operation during Idle mode and may generate interrupts to cause the processor to resume execution. Idle mode eliminates power used by the processor itself, memory systems and related controllers, and internal buses. In Power-down mode, the oscillator is shut down and the chip receives no internal clocks. The processor state and registers, peripheral registers, and internal SRAM values are preserved throughout Power-down mode and the logic levels of chip output pins remain static. The Power-down mode can be terminated and normal operation resumed by either a Reset or certain specific interrupts that are able to function without clocks. Since all dynamic operation of the chip is suspended, Power-down mode reduces chip power consumption to nearly zero. A Power Control for Peripherals feature allows individual peripherals to be turned off if they are not needed in the application, resulting in additional power savings.
6.21.7
VPB bus The VPB Divider determines the relationship between the processor clock (cclk) and the clock used by peripheral devices (PCLK). The VPB Divider serves two purposes. The first is that the VPB bus cannot operate at the highest speeds of the CPU. In order to compensate for this, the VPB bus may be slowed down to one half or one fourth of the processor clock rate. The default condition at reset is for the VPB bus to run at one quarter of the CPU clock. The second purpose of the VPB Divider is to allow power savings when an application does not require any peripherals to run at the full processor rate. Because the VPB Divider is connected to the PLL output, the PLL remains active (if it was running) during Idle mode.
6.22 Emulation and debugging
The LPC2292/LPC2294 support emulation and debugging via a JTAG serial port. A trace port allows tracing program execution. Debugging and trace functions are multiplexed only with GPIOs on Port 1. This means that all communication, timer and interface peripherals residing on Port 0 are available during the development and debugging phase as they are when the application is run in the embedded system itself. 6.22.1 Embedded ICETM Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of the target system requires a host computer running the debugger software and an EmbeddedICE protocol convertor. EmbeddedICE protocol convertor converts the Remote Debug Protocol commands to the JTAG data needed to access the ARM core.
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16/32-bit ARM microcontrollers with external memory interface
The ARM core has a Debug Communication Channel function built-in. The debug communication channel allows a program running on the target to communicate with the host debugger or another separate host without stopping the program flow or even entering the debug state. The debug communication channel is accessed as a co-processor 14 by the program running on the ARM7TDMI-S core. The debug communication channel allows the JTAG port to be used for sending and receiving data without affecting the normal program flow. The debug communication channel data and control registers are mapped in to addresses in the EmbeddedICETM logic. 6.22.2 Embedded trace Since the LPC2292/LPC2294 have significant amounts of on-chip memory, it is not possible to determine how the processor core is operating simply by observing the external pins. The Embedded Trace Macrocell provides real-time trace capability for deeply embedded processor cores. It outputs information about processor execution to the trace port. The ETM is connected directly to the ARM core and not to the main AMBA system bus. It compresses the trace information and exports it through a narrow trace port. An external trace port analyzer must capture the trace information under software debugger control. Instruction trace (or PC trace) shows the flow of execution of the processor and provides a list of all the instructions that were executed. Instruction trace is significantly compressed by only broadcasting branch addresses as well as a set of status signals that indicate the pipeline status on a cycle by cycle basis. Trace information generation can be controlled by selecting the trigger resource. Trigger resources include address comparators, counters and sequencers. Since trace information is compressed the software debugger requires a static image of the code being executed. Self-modifying code can not be traced because of this restriction. 6.22.3 RealMonitorTM RealMonitor is a configurable software module, developed by ARM Inc., which enables real time debug. It is a lightweight debug monitor that runs in the background while users debug their foreground application. It communicates with the host using the DCC (Debug Communications Channel), which is present in the EmbeddedICE logic. The LPC2292/LPC2294 contain a specific configuration of RealMonitor software programmed into the on-chip Flash memory.
7. Limiting values
Table 9: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V18 V3 V3A AVIN Vi Vi
9397 750 12748
Conditions
Min -0.5 -0.5 -0.5 -0.5 -0.5 -0.5
Max +2.5 +3.6 4.6 5.1 6.0
Unit V V V V V
Supply voltage, internal rail Supply voltage, external rail Analog 3.3 V pad supply voltage Analog input voltage on A/D related pins DC input voltage, 5 V tolerant I/O pins[3][4] DC input voltage, other I/O pins[2][3]
V3 + 0.5 V
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16/32-bit ARM microcontrollers with external memory interface
Table 9: Limiting values...continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter I I Tstg P DC supply current per supply pin[5] DC ground current per ground Storage temperature[6] pin[5] Conditions Min -40 1.5 Max 100 100 125 Unit mA mA C W
Power dissipation (based on package heat transfer, not device power consumption)
[1]
[2] [3] [4] [5] [6]
The following applies to the Limiting values: a) Stresses above those listed under Limiting values may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in Section 8 "Static characteristics" and Section 9 "Dynamic characteristics" of this specification is not implied. b) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. c) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. Not to exceed 4.6 V. Including voltage on outputs in 3-state mode. Only valid when the V3 supply voltage is present. The peak current is limited to 25 times the corresponding maximum current. Dependent on package type.
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16/32-bit ARM microcontrollers with external memory interface
8. Static characteristics
Table 10: Static characteristics Tamb = -40 C to +85 C for commercial, unless otherwise specified. Symbol Parameter V18 V3 V3A Supply voltage External rail supply voltage Analog 3.3 V pad supply voltage Low level input current, no pull-up High level input current, no pull down 3-state output leakage, no pull-up/down I/O latch-up current Input voltage[3][4][5] Output voltage, output active High level input voltage Low level input voltage Hysteresis voltage High level output Low level output voltage[6] voltage[6] IOH = -4 mA IOL = -4 mA VOH = V3 - 0.4 V VOL = 0.4 V VOH = 0 VOL = V3 Vi = 5 V[8] Vi = 0 V3 < Vi< 5 V[8] V18 = 1.8 V, cclk = 60 MHz, Tamb = 25 C, code while(1){} executed from FLASH, no active peripherals Power-down Mode V18 = 1.8 V, Tamb = +25 C, V18 = 1.8 V, Tamb = +85 C V18 = 1.8 V, Tamb = +105 C I2C pins VIH VIL
9397 750 12748
Conditions
Min 1.65 3.0 2.5
Typ[1] 1.8 3.3 3.3
Max 1.95 3.6 3.6
Unit V V V
Standard Port pins, RESET, RTCK IIL IIH IOZ Ilatchup Vi Vo VIH VIL Vhys VOH VOL IOH IOL IOH IOL IPD IPU I18 Vi = 0 Vi = V3 Vo = 0, Vo = V3 -(0.5 V3) < V < (1.5 V3) Tj < 125 C 0 0 2.0 V3 - 0.4 -4 4 10 -15 0 0.4 50 -50 0 30 5.5 V3 0.8 0.4 -45 50 150 -85 0 V V V V V V V mA mA mA mA A A A mA 100 3 3 3 A A A mA
High level output current[6] Low level output current[6] High level short circuit current[7] Low level short circuit current[7] Pull-down current Pull-up current (applies to P1.16 - P1.25) Active Mode
0.7 VTOL -
10/25[9] 50/110[9] 200[9] -
500 500 0.3 VTOL
A A A V V
High level input voltage Low level input voltage
VTOL is from 4.5 V to 5.5 V VTOL is from 4.5 V to 5.5 V
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16/32-bit ARM microcontrollers with external memory interface
Table 10: Static characteristics...continued Tamb = -40 C to +85 C for commercial, unless otherwise specified. Symbol Parameter Vhys VOL Ilkg Hysteresis voltage Low level output voltage[6] Input leakage to VSS Conditions VTOL is from 4.5 V to 5.5 V IOL = 3 mA Vi = V3 Vi = 5 V Oscillator pins X1 input Voltages X2 output Voltages
[1] [2] [3] [4] [5] [6] [7] [8] [9]
Min 0 0
Typ[1] 0.5 VTOL 2 10 -
Max 0.4 4 22 V18 V18
Unit V V A A
Typical ratings are not guaranteed. The values listed are at room temperature (+25 C), nominal supply voltages. Pin capacitance is characterized but not tested. Including voltage on outputs in 3-state mode. V3 supply voltages must be present. 3-state outputs go into 3-state mode when V3 is grounded. Accounts for 100 mV voltage drop in all supply lines. Only allowed for a short time period. Minimum condition for Vi = 4.5 V, maximum condition for Vi = 5.5 V. LPC2294 only.
Table 11: A/D converter DC electrical characteristics V3A = 2.5 V to 3.6 V unless otherwise specified; Tamb = -40 C to +85 C unless otherwise specified; A/D converter frequency 4.5 MHz. Symbol AVIN CIN DLe ILe OSe Ge Ae
[1] [2] [3] [4] [5] [6] [7]
Parameter Analog input voltage Analog input capacitance Differential Offset Gain non-linearity[1][2][3] Integral non-linearity[1][4] error[1][5] error[1][7] error[1][6]
Min 0 -
Max V3A 1 1 2 3 0.5 4
Unit V pF LSB LSB LSB % LSB
Absolute
Conditions: VSSA = 0 V, V3A = 3.3 V. The A/D is monotonic, there are no missing codes. The differential non-linearity (DLe) is the difference between the actual step width and the ideal step width. See Figure 4. The integral no-linearity (ILe) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 4. The offset error (OSe) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve. See Figure 4. The gain error (Ge) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See Figure 4. The absolute voltage error (Ae) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated A/D and the ideal transfer curve. See Figure 4.
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offset error OSe 1023
gain error Ge
1022
1021
1020
1019
1018 (2)
7 Code out 6 (1)
5 (5) 4 (4) 3 (3) 2
1
1 LSB (ideal) 1018 1019 1020 1021 1022 1023 1024
0 1 2 3 4 5 6 7 AVIN (LSBideal) offset error OSe
1 LSB =
V3A - VSSA 1024
002aaa668
(1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential non-linearity (DLe). (4) Integral non-linearity (ILe). (5) Center of a step of the actual transfer curve.
Fig 4. A/D conversion characteristics.
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9. Dynamic characteristics
Table 12: Characteristics Tamb = 0 C to +70 C for commercial, -40 C to +85 C for industrial, V18, V3 over specified ranges[1] Symbol External Clock fosc Oscillator frequency supplied by an external oscillator (signal generator) External clock frequency supplied by an external crystal oscillator External clock frequency if on-chip PLL is used External clock frequency if ISP is used for initial code download tC tCHCX tCLCX tCLCH tCHCL Port Pins tRISE tFALL I2C pins tf Output fall time from VIH to VIL 20 + 0.1 x Cb[2] ns Port output rise time (except P0.2, P0.3) Port output fall time (except P0.2, P0.3) 10 10 ns ns External oscillator clock period Clock high time Clock low time Clock rise time Clock fall time 1 1 10 10 20 tc x 0.4 tc x 0.4 50 30 25 25 1000 5 5 MHz MHz MHz MHz ns ns ns ns ns Parameter Conditions Min Typ[1] Max Unit
[1] [2]
Parameters are valid over operating temperature range unless otherwise specified. Bus capacitance Cb in pF, from 10 pF to 400 pF.
Table 13: Symbol tCHAVR tCHCSL tCHCSH tCHANV tCSLAV tOELAVR tCSLOEL tAVDV
External memory interface AC characteristics. CL = 25 pF. Tamb = 40 C Description XCLK HIGH to Address Valid XCLK HIGH to CS LOW XCLK HIGH to CS HIGH XCLK HIGH to Address Invalid CS LOW to Address Valid OE LOW to Address Valid CS LOW to OE LOW Memory Access Time (latest of Address Valid, CS LOW, OE LOW to Data Valid) Min -5[1] -5[1] -5 Max 10 10 10 10 10 10 5 Unit ns ns ns ns ns ns ns ns
Common to Read and Write Cycles
Read Cycle Parameters
(tCYC*(2 + WST1)) + (-20) -
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16/32-bit ARM microcontrollers with external memory interface
Table 13: Symbol tAVDV
External memory interface AC characteristics. CL = 25 pF. Tamb = 40 C...continued Description Burst-ROM Initial Memory Access Time (latest of Address Valid, CS LOW, OE LOW to Data Valid) Min Max Unit ns (tCYC*(2 + WST1)) + (-20) -
tAVDV tSTHDNV tCSHOEH tOEHANV tCHOEL tCHOEH tAVCSLW tCSLDVW tCSLWEL tCSLBLSL tWELDV tCSLDV tWELWEH tWELWEH tWEHANV tWEHDNV tBLSHANV tBLSHDNV tCHDV tCHWEL tCHHBLSL tAVCSL tAVCSL tAVCSL
[1]
Burst-ROM Subsequent Memory Access tCYC + (-20) Time (Address Valid to Data Valid) Data Hold Time (earliest of CS HIGH, OE 0 HIGH, Address Change to Data Invalid) CS HIGH to OE HIGH OE HIGH to Address Invalid XCLK HIGH to OE LOW XCLK HIGH to OE HIGH Address Valid to CS LOW CS LOW to Data Valid CS LOW to WE LOW CS LOW to BLS LOW WE LOW to Data Valid CS LOW to Data Valid WE LOW to WE HIGH BLS LOW to BLS HIGH WE HIGH to Address Invalid WE HIGH to Data Invalid BLS HIGH to Address Invalid BLS HIGH to Data Invalid XCLK HIGH to Data Valid XCLK HIGH to WE LOW XCLK HIGH to BLS LOW XCLK HIGH to WE HIGH XCLK HIGH to BLS HIGH XCLK HIGH to Data Invalid -5 -5 -5 -5 tCYC - 10 [1] -5 -5 -5 -5 -5 tCYC x (1 + WST2) - 5 tCYC x (1 + WST2) - 5 tCYC-5 (2 x tCYC)-5 tCYC-5 (2 x tCYC)-5 -
5 5 5 5 5 5 5 5 5 tCYC*(1 + WST2) + 5 tCYC*(1 + WST2) + 5 tCYC + 5 (2 x tCYC) + 5 tCYC + 5 (2 x tCYC) + 5 10 10 10 10 10 10
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Write Cycle Parameters
Except on initial access, in which case the address is set up tCYC earlier.
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Table 14:
Standard read access specifications Max frequency WST setting WST 0; round up to integer Memory access time requirement t RAM t CYC x ( 2 + WST 1 ) - 20ns t WRITE t CYC x ( 1 + WST 2 ) - 5ns t INIT t CYC x ( 2 + WST 1 ) - 20ns t ROM t CYC - 20ns
Access cycle
Standard read
2 + WST 1 f MAX -----------------------------t RAM + 20ns 1 + WST 2 f MAX ------------------------------t WRITE + 5ns 2 + WST 1 f MAX ----------------------------t INIT + 20ns 1 f MAX -----------------------------t ROM + 20ns
t RAM + 20ns WST 1 ------------------------------ - 2 t CYC t WRITE - t CYC + 5 WST 2 ------------------------------------------t CYC t INIT + 20ns WST 1 ----------------------------- - 2 t CYC N/A
Standard write
Burst read - initial
Burst read - subsequent 3x
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16/32-bit ARM microcontrollers with external memory interface
9.1 Timing
VDD - 0.5 V 0.45 V
0.2 VDD + 0.9 0.2 VDD - 0.1 V tCHCX
tCHCL
tCLCX
tC
tCLCH
002aaa416
Fig 5. External clock timing.
XCLK t CS t CLSAV CSHOEH
Addr t Data AVDV t STHDNV
t
CSLOEL t OELAVR t CHOEL t OEHANV t CHOEH
OE
002aaa749
Fig 6. External memory read access.
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XCLK
CS t AVCSLW
t CSLDVW t WELWEH t WEHANV t BLSHANV
BLS/WE
t t
CSLWEL
t BLSLBLSH t WELDV
CSLBLSL
Addr t Data t CSLDV WEHDNV
t BLSHDNV
OE
002aaa750
Fig 7. External memory write access.
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10. Package outline
LQFP144: plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm SOT486-1
c
y X
A 108 109 73 72 ZE
e
E HE
A A2
A1
(A 3) Lp L detail X
wM bp pin 1 index 144 1 wM D HD ZD B vM B 36 bp vM A 37
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.15 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D (1) 20.1 19.9 E (1) 20.1 19.9 e 0.5 HD HE L 1 Lp 0.75 0.45 v 0.2 w 0.08 y 0.08 Z D(1) Z E(1) 1.4 1.1 1.4 1.1 7o 0o
22.15 22.15 21.85 21.85
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT486-1 REFERENCES IEC 136E23 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-03-14 03-02-20
Fig 8.
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11. Revision history
Table 15: Rev Date 01 20040205 Revision history CPCN Description Preliminary data (9397 750 12748)
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12. Data sheet status
Level I II Data sheet status[1] Objective data Preliminary data Product status[2][3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
III
Product data
Production
[1] [2] [3]
Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
13. Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
15. Licenses
Purchase of Philips I2C components Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
14. Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
16. Trademarks
RealMonitor -- is a trademark of ARM, Inc. EmbeddedICE -- is a trademark of ARM, Inc. ARM7TDMI-S -- is a trademark of ARM, Inc. SPI -- is a trademark of Motorola, Inc.
Contact information
For additional information, please visit http://www.semiconductors.philips.com. For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.
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16/32-bit ARM microcontrollers with external memory interface
Contents
1 2 2.1 3 3.1 4 5 5.1 5.2 6 6.1 6.2 6.3 6.4 6.5 6.5.1 6.6 6.7 6.8 6.9 6.10 6.11 6.11.1 6.12 6.12.1 6.13 6.13.1 6.14 6.14.1 6.15 6.15.1 6.16 6.16.1 6.17 6.17.1 6.18 6.18.1 6.19 6.19.1 6.20 6.20.1 6.21 6.21.1 6.21.2 6.21.3 6.21.4 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . 11 Architectural overview. . . . . . . . . . . . . . . . . . . 11 On-Chip Flash program memory . . . . . . . . . . 11 On-Chip static RAM . . . . . . . . . . . . . . . . . . . . 11 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 12 Interrupt controller . . . . . . . . . . . . . . . . . . . . . 12 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 13 Pin connect block . . . . . . . . . . . . . . . . . . . . . . 14 Pin function select register 0 (PINSEL0 - 0xE002C000). . . . . . . . . . . . . . . . . . . . . . . . 14 Pin function select register 1 (PINSEL1 - 0xE002C004). . . . . . . . . . . . . . . . . . . . . . . . 16 Pin function select register 2 (PINSEL2 - 0xE002C014). . . . . . . . . . . . . . . . . . . . . . . . 18 External memory controller. . . . . . . . . . . . . . . 20 General purpose parallel I/O. . . . . . . . . . . . . . 20 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 10-bit A/D converter . . . . . . . . . . . . . . . . . . . . 20 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 CAN controllers and acceptance filter . . . . . . 20 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 I2C serial I/O controller . . . . . . . . . . . . . . . . . . 21 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 SPI serial I/O controller. . . . . . . . . . . . . . . . . . 21 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 General purpose timers . . . . . . . . . . . . . . . . . 22 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 22 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Real time clock . . . . . . . . . . . . . . . . . . . . . . . . 23 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Pulse width modulator . . . . . . . . . . . . . . . . . . 23 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 System control . . . . . . . . . . . . . . . . . . . . . . . . 24 Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . 24 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Reset and wake-up timer . . . . . . . . . . . . . . . . 25 External interrupt inputs . . . . . . . . . . . . . . . . . 25 6.21.5 6.21.6 6.21.7 6.22 6.22.1 6.22.2 6.22.3 7 8 9 9.1 10 11 12 13 14 15 16 Memory Mapping Control. . . . . . . . . . . . . . . . Power Control. . . . . . . . . . . . . . . . . . . . . . . . . VPB bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Emulation and debugging. . . . . . . . . . . . . . . . Embedded ICETM . . . . . . . . . . . . . . . . . . . . . . Embedded trace. . . . . . . . . . . . . . . . . . . . . . . RealMonitorTM . . . . . . . . . . . . . . . . . . . . . . . . Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Static characteristics . . . . . . . . . . . . . . . . . . . Dynamic characteristics . . . . . . . . . . . . . . . . . Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Data sheet status. . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 26 26 26 26 27 27 27 29 32 35 37 38 39 39 39 39 39
(c) Koninklijke Philips Electronics N.V. 2004. Printed in the U.S.A.
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 05 February 2004 Document order number: 9397 750 12748

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